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1-mbit (128k x 8) static ram cy62128bn mobl ? cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 001-06498 rev. *a revised august 3, 2006 features ? temperature ranges ? commercial: 0c to 70c ? industrial: ?40c to 85c ? automotive-a: ?40c to 85c ? automotive-e: ?40c to 125c ? 4.5v?5.5v operation ? cmos for optimum speed/power ? low active power (70 ns commercial, industrial, automotive-a) ? 82.5 mw (max.) (15 ma) ? low standby power (55/70 ns commercial, in dustrial, automotive-a) ?110 w (max.) (15 a) ? automatic power-down when deselected ? ttl-compatible inputs and outputs ? easy memory expansion with ce 1 , ce 2 , and oe options ? available in pb-free an d non-pb-free 32-pin (450 mil-wide) soic, 32-pin stsop and 32-pin tsop-i functional description [1] the cy62128bn is a high-per formance cmos static ram organized as 128k words by 8 bits. easy memory expansion is provided by an active low chip enable (ce 1 ), an active high chip enable (ce 2 ), an active low output enable (oe ), and tri-state drivers. this device has an automatic power-down feature that reduces power consumption by more than 75% when deselected. writing to the device is accomplished by taking chip enable one (ce 1 ) and write enable (we ) inputs low and chip enable two (ce 2 ) input high. data on the eight i/o pins (i/o 0 through i/o 7 ) is then written into the location specified on the address pins (a 0 through a 16 ). reading from the device is accomplished by taking chip enable one (ce 1 ) and output enable (oe ) low while forcing write enable (we ) and chip enable two (ce 2 ) high. under these conditions, the contents of the memory location specified by the address pins will appear on the i/o pins. the eight input/output pins (i/o 0 through i/o 7 ) are placed in a high-impedance state when the device is deselected (ce 1 high or ce 2 low), the outputs are disabled (oe high), or during a write operation (ce 1 low, ce 2 high, and we low). note: 1. for best-practice recommendations, please refer to the cypress application note ?system design guidelines? on http://www.cypr ess.com. 14 15 logic block diagram a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 column decoder row decoder sense amps input buffer power down we oe i/o 0 ce 2 i/o 1 i/o 2 i/o 3 128k x 8 array i/o 7 i/o 6 i/o 5 i/o 4 a 0 a 11 a 13 a 12 a a 10 ce 1 a a 16 a 9 1 2 3 4 5 6 7 8 9 10 11 14 19 20 24 23 22 21 25 28 27 26 top view 12 13 29 32 31 30 16 15 17 18 a 16 a 14 a 12 a 7 a 6 a 5 a 4 a 3 we v cc a 15 a 13 a 8 a 9 i/o 7 i/o 6 i/o 5 i/o 4 a 2 nc i/o 0 i/o 1 i/o 2 ce 1 oe a 10 i/o 3 a 1 a 0 a 11 ce 2 soic gn gnc g g gnd pin configuration [+] feedback [+] feedback
cy62128bn mobl ? document #: 001-06498 rev. *a page 2 of 12 pin configurations product portfolio product v cc range (v) speed (ns) power dissipation operating, i cc (ma) standby, i sb2 ( a) min. typ. [2] max. typ. [2] max. typ. [2] max. cy62128bnll commercial 4.5 5.0 5.5 55 7.5 20 2.5 15 70 6 15 2.5 15 industrial 55 7.5 20 2.5 15 70 6 15 2.5 15 automotive-a 70 6 15 2.5 15 automotive-e 70 6 25 2.5 25 pin definitions input a 0 ?a 16 . address inputs input/output i/o 0 ?i/o 7 . data lines. used as input or output lines depending on operation input/control we . write enable, active low. when selected low, a write is conducted. when selected high, a read is conducted. input/control ce 1 . chip enable 1, active low. input/control ce 2 . chip enable 2, active high. input/control oe . output enable, active low. cont rols the direction of the i/o pins . when low, the i/o pins behave as outputs. when deasserted high, i/o pins ar e tri-stated, and act as input data pins ground gnd . ground for the device power supply v cc . power supply for the device note: 2. typical values are included for reference only and are not te sted or guaranteed. typical values are an average of the distrib ution across normal production variations as measured at v cc = 5.0v, t a = 25c, and t aa = 70 ns. a 6 a 7 a 16 a 14 a 12 we v cc a 4 a 13 a 8 a 9 oe tsop i top view (not to scale) 1 6 2 3 4 5 7 32 27 31 30 29 28 26 21 24 23 22 19 20 i/o 2 i/o 1 gnd i/o 7 i/o 4 i/o 5 i/o 0 ce 1 a 11 a 5 17 18 8 9 10 11 12 13 14 15 16 ce 2 a 15 nc a 10 i/o 3 a 1 a 0 a 3 a 2 a 6 a 7 a 16 a 14 a 12 we v cc a 4 a 13 a 8 a 9 oe stsop top view (not to scale) 25 30 26 27 28 29 31 24 19 23 22 21 20 18 13 17 16 15 14 11 12 i/o 2 i/o 1 gnd i/o 7 i/o 4 i/o 5 i/o 6 i/o 0 ce 1 a 11 a 5 9 10 32 1 2 3 4 5 6 7 8 ce 2 a 15 nc a 10 i/o 3 a 1 a 0 a 3 a 2 i/o 6 25 [+] feedback [+] feedback
cy62128bn mobl ? document #: 001-06498 rev. *a page 3 of 12 maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature ................................. ?65 c to +150 c ambient temperature with power applied............................................. ?55 c to +125 c supply voltage on v cc to relative gnd [3] .... ?0.5v to +7.0v dc voltage applied to outputs in high-z state [3] ....................................?0.5v to v cc + 0.5v dc input voltage [3] .................................?0.5v to v cc + 0.5v current into outputs (low) .... .....................................20 ma static discharge voltage......... .............. .............. ...... > 2001v (per mil-std-883, method 3015) latch-up current..................................................... > 200 ma operating range range ambient temperature (t a ) [4] v cc commercial 0 c to +70 c 5v 10% industrial ?40 c to +85 c automotive-a ?40 c to +85 c automotive-e ?40 c to +125 c electrical characteristics over the operating range parameter description test conditions -55 -70 unit min. typ. [2] max. min. typ. [2] max. v oh output high voltage v cc = min., i oh = ?1.0 ma 2.4 2.4 v v ol output low voltage v cc = min., i ol = 2.1 ma 0.4 0.4 v v ih input high voltage 2.2 v cc + 0.3 2.2 v cc + 0.3 v v il input low voltage [3] ?0.3 0.8 ?0.3 0.8 v i ix input leakage current gnd v i v cc commercial/ industrial ?1 +1 ?1 +1 a automotive-a ?1 +1 a automotive-e ?10 +10 a i oz output leakage current gnd v i v cc , output disabled commercial/ industrial ?1 +1 ?1 +1 a automotive-a ?1 +1 a automotive-e ?10 +10 a i cc v cc operating supply current v cc = max., i out = 0 ma, f = f max = 1/t rc commercial/ industrial 7.5 20 6 15 ma automotive-a 615ma automotive-e 625ma i sb1 automatic ce power-down current ?ttl inputs max. v cc , ce 1 v ih or ce 2 < v il , v in v ih or v in v il , f = f max commercial/ industrial 0.1 20.11ma automotive-a 0.1 1 ma automotive-e 0.1 2 ma i sb2 automatic ce power-down current ?cmos inputs max. v cc , ce 1 v cc ? 0.3v, or ce 2 0.3v, v in v cc ? 0.3v, or v in 0.3v, f = 0 commercial/ industrial 2.5 15 2.5 15 a automotive-a 2.5 15 a automotive-e 2.5 25 a notes: 3. v il (min.) = ?2.0v for pulse durations of less than 20 ns. 4. t a is the ?instant on? case temperature. [+] feedback [+] feedback
cy62128bn mobl ? document #: 001-06498 rev. *a page 4 of 12 capacitance [5] parameter description test conditions max. unit c in input capacitance t a = 25 c, f = 1 mhz, v cc = 5.0v 9pf c out output capacitance 9 pf thermal resistance [5] parameter description test conditions 32 soic 32 stsop 32 tsop unit ja thermal resistance (junction to ambient) test conditions follow standard test methods and procedures for measuring thermal impedance, per eia / jesd51. 66.17 105.14 97.44 c/w jc thermal resistance (junction to case) 30.87 14.09 26.05 c/w ac test loads and waveforms 90% 10% v cc gnd 90% 10% all input pulses 5v output 100 pf including jig and scope 5v output 5 pf including jig and scope (a) (b) output r1 1800 ? r1 1800 ? r2 990 ? r2 990 ? 639 ? equivalent to: thvenin equivalent 1.77v rise time: 1 v/ns fall time : 1 v/ns data retention waveform data retention characteristics (over the operating range) parameter description conditions [6] min. typ. max. unit v dr v cc for data retention 2.0 v i ccdr data retention current v cc = v dr = 2.0v, ce 1 v cc ? 0.3v, or ce 2 0.3v, v in v cc ? 0.3v or, v in 0.3v commercial/ industrial automotive-a 1.5 15 a automotive-e 1.5 25 a t cdr chip deselect to data retention time 0ns t r operation recovery time 70 ns note: 5. tested initially and after any design or process changes that may affect these parameters. 6. no input may exceed v cc + 0.5v. v cc , min. v cc , min. t cdr v dr > 2v t r ce 1 v cc ce 2 or data retention mode [+] feedback [+] feedback
cy62128bn mobl ? document #: 001-06498 rev. *a page 5 of 12 switching characteristics [7] over the operating range parameter description cy62128bn-55 cy62128bn-70 unit min. max. min. max. read cycle t rc read cycle time 55 70 ns t aa address to data valid 55 70 ns t oha data hold from address change 5 5 ns t ace ce 1 low to data valid, ce 2 high to data valid 55 70 ns t doe oe low to data valid 20 35 ns t lzoe oe low to low z 0 0 ns t hzoe oe high to high z [7, 9] 20 25 ns t lzce ce 1 low to low z, ce 2 high to low z [9] 55ns t hzce ce 1 high to high z, ce 2 low to high z [8, 9] 20 25 ns t pu ce 1 low to power-up, ce 2 high to power-up 0 0 ns t pd ce 1 high to power-down, ce 2 low to power-down 55 70 ns write cycle [10] t wc write cycle time 55 70 ns t sce ce 1 low to write end, ce 2 high to write end 45 60 ns t aw address set-up to write end 45 60 ns t ha address hold from write end 0 0 ns t sa address set-up to write start 0 0 ns t pwe we pulse width 45 50 ns t sd data set-up to write end 25 30 ns t hd data hold from write end 0 0 ns t lzwe we high to low z [9] 55ns t hzwe we low to high z [8, 9] 20 25 ns switching waveforms read cycle no.1 [11, 12] notes: 7. test conditions assume signal transition ti me of 5 ns or less, timing reference levels of 1.5v, input pulse levels of 0 to 3. 0v, and output loading of the specified i ol /i oh and 100-pf load capacitance. 8. t hzoe , t hzce , and t hzwe are specified with a load capacitance of 5 pf as in (b) of ac test loads. transition is measured 500 mv from steady-state voltage. 9. at any given temperature and voltage condition, t hzce is less than t lzce , t hzoe is less than t lzoe , and t hzwe is less than t lzwe for any given device. 10. the internal write time of the memory is defined by the overlap of ce 1 low, ce 2 high, and we low. ce 1 and we must be low and ce 2 high to initiate a write, and the transition of any of these signals can terminate the write. the input data set-up and hold timing should be refe renced to the leading edge of the signal that terminates the write. 11. device is continuously selected. oe , ce 1 = v il , ce 2 = v ih . 12. we is high for read cycle. previous data valid data valid t rc t aa t oha address data out [+] feedback [+] feedback
cy62128bn mobl ? document #: 001-06498 rev. *a page 6 of 12 read cycle no. 2 (oe controlled) [12, 13] write cycle no. 1 (ce 1 or ce 2 controlled) [14, 15] notes: 13. address valid prior to or coincident with ce 1 transition low and ce 2 transition high. 14. data i/o is high impedance if oe = v ih . 15. if ce 1 goes high or ce 2 goes low simultaneously with we going high, the output remains in a high-impedance state. switching waveforms (continued) 50% 50% data valid t rc t ace t doe t lzoe t lzce t pu high impedance t hzoe t hzce t pd high oe ce 1 i cc i sb impedance address ce 2 data out v cc supply current t wc data valid t aw t sa t pwe t ha t hd t sd t sce t sce ce 1 address ce 2 we data i/o [+] feedback [+] feedback
cy62128bn mobl ? document #: 001-06498 rev. *a page 7 of 12 write cycle no. 2 (we controlled, oe high during write) [14, 15] write cycle no.3 (we controlled, oe low) [14, 15] note: 16. during this period the i/os are in the output state and input signals should not be applied. switching waveforms (continued) t hd t sd t pwe t sa t ha t aw t sce t sce t wc t hzoe data in valid ce 1 address ce 2 we data i/o oe note 16 data valid t hd t sd t lzwe t pwe t sa t ha t aw t sce t sce t wc t hzwe ce 1 address ce 2 we data i/o note 16 [+] feedback [+] feedback
cy62128bn mobl ? document #: 001-06498 rev. *a page 8 of 12 truth table ce 1 ce 2 oe we i/o 0 ?i/o 7 mode power h x x x high z power-down standby (i sb ) x l x x high z power-down standby (i sb ) lhlhdata out read active (i cc ) l h x l data in write active (i cc ) l h h h high z selected, outputs disabled active (i cc ) ordering information speed (ns) ordering code package diagram package type operating range 55 cy62128bnll-55sc 51-85081 32-pin 450-mil soic commercial cy62128bnll-55sxc 32-pin 450-mil soic (pb-free) cy62128bnll-55si 32-pin 450-mil soic industrial cy62128bnll-55sxi 32-pin 450-mil soic (pb-free) cy62128bnll-55zai 51-85094 32-pin stsop cy62128bnll-55zaxi 32-pin stsop (pb-free) cy62128bnll-55zi 51-85056 32-pin tsop type i cy62128bnll-55zxi 32-pin tsop type i (pb-free) 70 cy62128bnll-70sc 51-85081 32-pin 450-mil soic commercial cy62128bnll-70sxc 32-pin 450-mil soic (pb-free) CY62128BNLL-70ZC 51-85056 32-pin tsop type i cy62128bnll-70zxc 32-pin tsop type i (pb-free) cy62128bnll-70si 51-85081 32-pin 450-mil soic industrial cy62128bnll-70sxi 32-pin 450-mil soic (pb-free) cy62128bnll-70zai 51-85094 32-pin stsop cy62128bnll-70zaxi 32-pin stsop (pb-free) cy62128bnll-70zi 51-85056 32-pin tsop type i cy62128bnll-70zxi 32-pin tsop type i (pb-free) cy62128bnll-70zxa 51-85056 32-pin tsop type i (pb-free) automotive-a cy62128bnll-70sxa 51-85081 32-pin 450-mil soic (pb-free) cy62128bnll-70sxe 51-85081 32-pin 450 -mil soic (pb-free) automotive-e cy62128bnll-70zaxe 51-85094 32-pin stsop (pb-free) please contact your local cypress sales r epresentative for availability of these parts [+] feedback [+] feedback
cy62128bn mobl ? document #: 001-06498 rev. *a page 9 of 12 package diagrams 0.546[13.868] 0.440[11.176] 0.101[2.565] 0.050[1.270] 0.014[0.355] 0.118[2.997] 0.004[0.102] 0.047[1.193] 0.006[0.152] 0.023[0.584] 0.793[20.142] 0.450[11.430] 0.566[14.376] 0.111[2.819] 0.817[20.751] bsc. 0.020[0.508] min. max. 0.012[0.304] 0.039[0.990] 0.063[1.600] seating plane 1 16 17 32 0.004[0.102] 51-85081-*b 32-pin (450 m il) molded soic (51-85081) [+] feedback [+] feedback
cy62128bn mobl ? document #: 001-06498 rev. *a page 10 of 12 package diagrams (continued) 32-pin stsop (8 x 13.4 mm) (51-85094) 51-85094-*d [+] feedback [+] feedback
cy62128bn mobl ? document #: 001-06498 rev. *a page 11 of 12 ? cypress semiconductor corporation, 2006. the information contained herein is subject to change without notice. cypress semic onductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or ot her rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agr eement with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to re sult in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manu facturer assumes all risk of such use and in doing so indemni fies cypress against all charges. all product and company names mentio ned in this document are the tradema rks of their respective holders. package diagrams (continued) 51-85056-*d 32-pin tsop type i (8 x 20 mm) (51-85056) [+] feedback [+] feedback
cy62128bn mobl ? document #: 001-06498 rev. *a page 12 of 12 document history page document title: cy62128bn mobl ? 1-mbit (128k x 8) static ram document number: 001-06498 rev. ecn no. issue date orig. of change description of change ** 426503 see ecn nxr new data sheet *a 488954 see ecn nxr added automotive product removed rtsop package updated ordering information table [+] feedback [+] feedback

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